US patent application publication US 2006-0145252 describes a transistor power switch device comprising an array of vertical insulated gate ‘MOSFET’s. Its operating characteristics of the transistor power switch device are basically very satisfactory for example in terms of ON resistance and stand-off voltage. Like other transistor power switch devices it is subject to avalanche breakdown in certain circumstances, however.
Avalanche breakdown is a phenomenon that can occur in both insulating and semiconducting materials. It is a form of electric current multiplication that can allow very large currents to flow within materials which are otherwise good insulators when the electric field in the material is great enough to accelerate free electrons to the point that, when they strike atoms in the material, they can knock other electrons free: the number of free electrons is thus increased rapidly as newly generated particles become part of the process. This phenomenon can pose an upper limit on operating voltages since the associated electric fields can induce the electric current multiplication and cause excessive (if not unlimited) current flow and destruction of the device.
Avalanche breakdown of a transistor power switch is liable to be caused by unclamped inductive switching (‘UIS’). Power transistors such as metal-oxide-silicon field-effect transistors (‘MOSFET’s) inherently have extremely fast switching speeds. The fast switching speeds can lead to device stress not normally encountered in slower switching circuits. In fact, switching speeds may be so fast that at device turn-off, small parasitic inductance in the circuit can lead to significant over voltage transients. If the resulting voltage transient is large enough, the switching transistor may be forced into avalanche, such as drain-to-source avalanche in the case of a MOSFET. Transistors may be required to withstand large numbers of repetitive avalanche breakdown occurrences without failure.
US patent application publication 20070176231 describes a MOSFET transistor power switch device in which some of the transistor cells have different mesa (regions between trench gates) sizes. A heavy body etch is utilized in larger transistor cells to reduce the pinched-base resistance. This etch removes silicon in the mesa region, which is then replaced with lower-impedance aluminum. A number of smaller transistor cells that do not receive this etch are used to increase device current capacity. Avalanche current is directed to the larger, lower pinched base cells by ensuring these cells have a lower BVDSS breakdown voltage, giving a measure of avalanche protection to the smaller cells.